Department of ECE, Maharaja Agrasen Institute of Technology (M.A.I.T.) conducted a one week Faculty Development Program on “VLSI Design & Modeling (Short Intensive Course)”, which was held from 6th May. 2019 to 11th May 2019 at M.A.I.T campus. This Faculty Development Programme (FDP) aimed at honing the teaching and research skills of prospective, new and seasoned management teachers, researchers in the field of VLSI Design and Modeling. The keynote speakers during the FDP were Prof. R.S.Gupta (ECE Department, MAIT), Dr. P.K. Saxena (Tech Next Lab Pvt. Ltd.), Dr. Yogesh Pratap (Delhi University) and Dr. Manoj Kumar (Post Doctoral Fellow, Dept. of Electrical Engg., IIT Delhi). Lab sessions were taken by Mr. Harendra Kumar (Synopsis), Mr. Ankush Singh and Mr. Mayank Singh (CoreEL), Dr. Sonam Rewari and Mr. Nitin Trivedi (M.A.I.T.). The program was attended by 63 faculties/Research Scholars. 20 attendees were from different academic institutions like Delhi Technological University, Delhi University, IIIT Delhi and colleges affiliated to Guru Gobind Singh Indraprastha University.